The present invention relates generally to a semiconductor memory device and a method of operating the same, and more specifically a semiconductor memory device designed for an erase operation, and a method of operating the same.
A semiconductor memory device may include a memory cell array in which data is stored, which may include a plurality of memory cell blocks, which in turn may include a plurality of cell strings in which memory cells are included. Memory cells included in different cell strings may be connected to a plurality of word lines, and those connected to the same word line may be called a page. Accordingly, one memory cell block may include the same number of pages as word lines.
A semiconductor memory device may perform an erase operation on one memory cell block selected out of a plurality of memory cell blocks. An erase operation may be performed when a ground voltage (about 0V) is applied to all word lines of the selected memory cell block, which are floating, and an erase voltage is applied to a well of the selected memory cell block.
To improve the distribution of threshold voltages of memory cells, an erase operation has been performed by gradually elevating the erase voltage using an incremental step pulse erase (ISPE) process. While an ISPE erase operation contributes towards improving the distribution of threshold voltages of memory cells, there is a limitation for improving the distribution of threshold voltages of erased memory cells due to the increase in integration density of semiconductor memory devices.